DSP56857 datasheet(562/662 Pages) FREESCALE

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Sheet

5685X Digital Signal Controller User Manual, Rev. 4

B-60

Freescale Semiconductor

SCI Status Register

(SCISR)

Base + $3

Bits

Read TDRE TIDLE RDRF RIDLE OR

RAF

Write

Reset

0000

000

Bits

Name

Description

Framing Error

This bit is set when a Logic 0 is accepted as the stop bit. The FE bit is set during the same cycle

as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception

until it is cleared. Clear FE by reading the SCI Status Register (SCISR) with FE set and then

writing the SCI status register with any value.

No framing error

Framing error

Parity Error Flag

This bit is set when the parity enable PE bit is set and the parity of the received data does not

match its parity bit. Clear PF by reading the SCI Status Register (SCISR) and then writing the SCI

status register with any value.

No parity error

Parity error

RAF

Receiver Active Flag

This bit is set when the receiver detects a Logic 0 during the RT1 time period of the start bit search.

RAF is cleared when the receiver detects false start bits (usually from noise or baud rate

mismatch) or when the receiver detects a preamble.

No reception in progress

Reception in progress

denotes Reserved Bits

8 of 9

SCI

SCI Status Register (SCISR) continued

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