SSD1963QL9R datasheet(37/93 Pages) ETC2

37 / 93 page

SSD1963

Rev 1.1

P 37/93

Jan 2010

Solomon Systech

Figure 9-11: A[7] Page Address Order

A[7]=0,

A[6]=A[5]=0,A[3]=x

A[7]=1,

A[6]=A[5]=0,A[3]=x

Host

Frame Buffer

Host

Frame Buffer



A[6] : Column address order (POR = 0)

This bit controls the order that columns of data are transferred from the host processor to the SSD1963’s frame buffer.

Left to right, columns transferred from SC (Start Column) to EC (End Column).

Right to left, columns transferred from EC (End Column) to SC (Start Column).

Figure 9-12: A[6] Column Address Order

A[6]=0,

A[7]=A[5]=0,A[3]=x

A[6]=1,

A[7]=A[5]=0,A[3]=x

Host

Frame Buffer

Host

Frame Buffer



A[5] : Page / Column order (POR = 0)

This bit controls the order that columns of data are transferred from the host processor to the SSD1963’s frame buffer.

Normal mode

Reverse mode

Figure 9-13: A[5] Page / Column Address Order

A[5]=0,

A[7]=A[6]=0,A[3]=x

A[5]=1,

A[7]=A[6]=0,A[3]=x

Host

Frame Buffer

Host

Frame Buffer



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