SSD1963QL9R datasheet(82/93 Pages) ETC2

82 / 93 page

Solomon Systech

Jan 2010

P 82/93

Rev 1.1

SSD1963

Table 13-5: Parallel 6800-series Interface Timing Characteristics (Use E as clock)

Symbol

Parameter

Min

Typ

Max

Unit

fMCLK

System Clock Frequency*

110

MHz

tMCLK

System Clock Period*

1/ fMCLK

tPWCSH

Control Pulse Low Width Write (next write cycle)

Write (next read cycle)

Read

1.5* tMCLK

9* tMCLK

tPWCSL

Control Pulse High Width Write

Read

1.5* tMCLK

3.5* tMCLK

tAS

Address Setup Time

tAH

Address Hold Time

tDSW

Data Setup Time

tDHW

Data Hold Time

tPLW

Write Low Time

tPHW

Write High Time

tPLWR

Read Low Time

tACC

Data Access Time

tDHR

Output Hold time

Rise Time

0.5

Fall Time

0.5

* System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled)

Figure 13-2: Parallel 6800-series Interface Timing Diagram (Use E as Clock)

D[17:0]

(WRITE)

D[17:0]

(READ)

tDHW

tACC

tDHR

Valid Data

tDSW

Valid Data

tAH

tAS

D/C

R/W

CS#

tPWCSL

tPWCSH

tPHWR / tPHW

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