845GL datasheet(68/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.1.23

ESMRAMC—Extended System Management RAM Control Register

(Device 0)

Address Offset:

9Eh

Default Value:

38h

Access:

R/W, R/WC, RO, L

Size:

8 bits

The Extended SMRAM register controls the configuration of Extended SMRAM space. The

Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory

space that is above 1 MB.

Note: When Extended SMRAM is used, the maximum amount of SDRAM accessible is limited to

256 MB.

Bit

Description

Enable High SMRAM (H_SMRAME)—R/W, L.

This bit controls the SMM memory space location

(i.e., above 1 MB or below 1 MB).

0 = Disable

1 = Enable. When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM memory

space is enabled. SMRAM accesses within the range 0FEDA0000h to 0FEDBFFFFh are

remapped to SDRAM addresses within the range 000A0000h to 000BFFFFh.

NOTE:

Once D_LCK has been set, this bit becomes read only.

Invalid SMRAM Access (E_SMERR)—R/WC.

0 = Software must write a 1 to this bit to clear it.

1 = This bit is set when processor has accessed the defined memory ranges in Extended SMRAM

(High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0.

SMRAM Cacheable (SM_CACHE)—RO.

Hardwired to 1.

L1 Cache Enable for SMRAM (SM_L1)—RO.

Hardwired to 1.

L2 Cache Enable for SMRAM (SM_L2)—RO.

Hardwired to 1.

2:1

TSEG Size (TSEG_SZ)—R/W, L.

This field selects the size of the TSEG memory block if enabled.

This memory is taken from the top of SDRAM space (TOM – TSEG_SZ), which is no longer claimed

by the memory controller (all accesses to this space are sent to the hub interface if TSEG_EN is set).

00 = Reserved

01 = Reserved

10 = (TOM – 512 k) to TOM

11 = (TOM – 1 M) to TOM

NOTE:

Once D_LCK is set, this bit becomes read only.

TSEG Enable (TSEG_EN)—R/W, L.

0 = Disable.

1 = Enable. Enabling of SMRAM memory for Extended SMRAM space only. When

G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical

address space.

NOTE:

Once D_LCK is set, this bit becomes read only.

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