845GL datasheet(32/193 Pages) INTEL

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Signal Description

Intel® 82845G/82845GL/82845GV GMCH Datasheet

2.4.6

PCI Pins during PCI Transactions on AGP Interface

The PCI signals described in Section 2.4.5 behave according to PCI Local Bus Specification,

Revision 2.1, when used to perform PCI transactions on the AGP Interface.

2.5

Multiplexed Intel® DVO Device Signal Interfaces

The DVO signals, described in the following table, are multiplexed with the AGP signals.

Name

Type

Description

DVOB_CLK;

DVOB_CLK#

AGP

DVOB Clock Output: These signals provide a differential pair reference

clock that can run up to 165 MHz. Formerly known by:

DVOB_CLKOUT0=DVOB_CLK and DVOB_CLKOUT1=DVOB_CLK#. Care

should be taken to be sure that DVOB_CLK is connected to the primary clock

receiver of the Intel® DVO device.

DVOB_D[11:0]

AGP

DVOB Data: This data bus is used to drive 12-bit pixel data on each edge of

DVOB_CLK(#). This provides 24 bits of data per clock.

DVOB_HSYNC

AGP

Horizontal Sync: This is the HSYNC signal for the DVOB interface. The

active polarity of the signal is programmable.

DVOB_VSYNC

AGP

Vertical Sync: This is the VSYNC signal for the DVOB interface. The active

polarity of the signal is programmable.

DVOB_BLANK#

AGP

Flicker Blank or Border Period Indication: DVOB_BLANK# is a

programmable output pin driven by the GMCH. When programmed as a

blank period indication, this pin indicates active pixels excluding the border.

When programmed as a border period indication, this pin indicates active

pixel including the border pixels.

DVOBC_CLKINT#

AGP

DVOBC Pixel Clock Input/Interrupt: This signal may be selected as the

reference input to the dot clock PLL (DPLL) for the multiplexed DVO devices.

This pin may also be programmed to be an interrupt input for either of the

multiplexed DVO devices.

DVOB_FLDSTL

AGP

TV Field and Flat Panel Stall Signal: This input can be programmed to be

either a TV Field input from the TV encoder or Stall input from the flat panel.

When used as a Field input, it synchronizes the overlay field with the TV

encoder field when the overlay is displaying an interleaved source. When

used as the Stall input, it indicates that the pixel pipeline should stall one

horizontal line. The polarity is programmable for both modes and the input

may be disabled completely.

DVOC_CLK;

DVOC_CLK#

AGP

DVOC Clock Output: These pins provide a differential pair reference clock

that can run up to 165 MHz. Formerly known by:

DVOC_CLKOUT0=DVOC_CLK and DVOC_CLKOUT1=DVOC_CLK#. Care

should be taken to be sure that DVOC_CLK is connected to the primary

clock receiver of the DVO device.

DVOC_D[11:0]

AGP

DVOC Data: This data bus is used to drive 12-bit pixel data on each edge of

DVOC_CLK(#). This provides 24 bits of data per clock.

DVOC_HSYNC

AGP

Horizontal Sync: This is the HSYNC signal for the DVOC interface. The

active polarity of the signal is programmable.

DVOC_VSYNC

AGP

Vertical Sync: This is the VSYNC signal for the DVOC interface. The active

polarity of the signal is programmable.

DVOC_BLANK#

AGP

Flicker Blank or Border Period Indication: DVOC_BLANK# is a

programmable output pin driven by the GMCH. When programmed as a

blank period indication, this signal indicates active pixels excluding the

border. When programmed as a border period indication, this signal indicates

active pixel including the border pixels.

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