845GL datasheet(24/193 Pages) INTEL

24 / 193 page

Signal Description

Intel® 82845G/82845GL/82845GV GMCH Datasheet

HDSTB_P[3:0]#

HDSTB_N[3:0]#

I/O

AGTL+

Differential Host Data Strobes: HDSTB_P[3:0]# and HDSTB_N[3:0]# are the

differential source synchronous strobes used to transfer HD_[63:0]# and

DINV_[3:0]# at the 4X transfer rate.

Strobe

Data Bits

HDSTB_P3#, HDSTB_N3#

HD_[63:48]#, DINV_3#

HDSTB_P2#, HDSTB_N2#

HD_[47:32]#, DINV_2#

HDSTB_P1#, HDSTB_N1#

HD_[31:16]#, DINV_1#

HDSTB_P0#, HDSTB_N0#

HD_[15:0]#, DINV_0#

HIT#

I/O

AGTL+

Hit: This signal indicates that a caching agent holds an unmodified version of

the requested line. Also, driven in conjunction with HITM# by the target to

extend the snoop window.

HITM#

I/O

AGTL+

Hit Modified: This signal indicates that a caching agent holds a modified

version of the requested line and that this agent assumes responsibility for

providing the line. HITM# is also driven in conjunction with HIT# to extend the

snoop window.

HLOCK#

AGTL+

Host Lock: All processor bus cycles sampled with the assertion of HLOCK#

and ADS#, until the negation of HLOCK# must be atomic (i.e., no hub interface

or AGP snoopable access to SDRAM are allowed when HLOCK# is asserted

by the processor).

HREQ_[4:0]#

I/O

AGTL+

Host Request Command: These signals define the attributes of the request.

HREQ_[4:0]# are transferred at 2X rate. They are asserted by the requesting

agent during both halves of Request Phase. In the first half the signals define

the transaction type to a level of detail that is sufficient to begin a snoop

request. In the second half the signals carry additional information to define the

complete transaction type.

The transactions supported by the GMCH Host Bridge are defined in

Section 4.1.

HTRDY#

AGTL+

Host Target Ready: This signal indicates that the target of the processor

transaction is able to enter the data transfer phase.

RS_[2:0]#

AGTL+

Response Signals: RS_[2:0]# indicate the type of response according to the

encoding below:

000 = Idle state

001 = Retry response

010 = Deferred response

011 = Reserved (not driven by GMCH)

100 = Hard Failure (not driven by GMCH)

101 = No data response

110 = Implicit Writeback

111 = Normal data response

Signal Name

Type

Description

845GL 데이터시트(PDF) 24 Page - Intel Corporation

845GL 데이터시트(HTML) 24 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL