845GL datasheet(75/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.1.34

ERRCMD—Error Command Register (Device 0)

Address Offset:

CA–CBh

Default Value:

0000h

Access:

RO, R/W

Size:

16 bits

This register controls the GMCH responses to various system errors. Since the GMCH does not

have an SERR# signal, SERR messages are passed from the GMCH to the ICH over HI. When a

bit in this register is set, a SERR message will be generated on HI whenever the corresponding flag

is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for

Device 0 via the PCI Command register.

Bit

Description

15:10

Intel Reserved.

SERR on Non-DRAM Lock (LCKERR).

1 = Disable.

1 = Enable. GMCH generates a HI SERR special cycle when a processor lock cycle is detected that

does not hit SDRAM.

8:7

Intel Reserved.

SERR on Target Abort on HI Exception (TAHLA).

0 = Disable.

1 = Enable. GMCH generates an SERR special cycle over HI when an GMCH originated HI cycle is

completed with a Target Abort completion packet or special cycle.

SERR on Detecting HI Unimplemented Special Cycle (HIAUSCERR).

SERR messaging for

Device 0 is globally enabled in the PCICMD register.

0 = Disable. GMCH does not generate an SERR message for this event.

1 = Enable. GMCH generates an SERR message over HI when an Unimplemented Special Cycle is

received on the HI.

SERR on AGP Access Outside of Graphics Aperture (OOGF).

0 = Disable. Reporting of this condition is disabled.

1 = Enable. GMCH generates an SERR special cycle over HI when an AGP access occurs to an

address outside of the graphics aperture.

SERR on Invalid AGP Access (IAAF).

0 = Disable. Invalid AGP Access condition is not reported.

1 = Enable. GMCH generates an SERR special cycle over HI when an AGP access occurs to an

address outside of the graphics aperture and either to the 640 KB –1 MB range or above the top

of memory. I

SERR on Invalid Translation Table Entry (ITTEF).

0 = Disable. Reporting of this condition is disabled.

1 = Enable. GMCH generates an SERR special cycle over HI when an invalid translation table entry

was returned in response to an AGP access to the graphics aperture.

1:0

Intel Reserved.

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