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845GL 데이터시트(PDF) 38 Page - Intel Corporation

부품명 845GL
상세설명  Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
PDF  193 Pages
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제조업체  INTEL [Intel Corporation]
홈페이지  http://www.intel.com
Logo INTEL - Intel Corporation

845GL 데이터시트(HTML) 38 Page - Intel Corporation

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Signal Description
38
Intel® 82845G/82845GL/82845GV GMCH Datasheet
2.10
Functional Straps
2.11
GMCH Sequencing Requirements
Power Plane and Sequencing Requirements:
• Clock Valid Timing:
• GCLKIN must be valid at least 10 µs prior to the rising edge of PWROK.
• HCLKN/HCLKP must be valid at least 10 µs prior to the rising edge of RSTIN#.
• There is no DREFCLK timing requirements relative to reset.
Signal Name
Type
Description
PSBSEL
I
PSB Frequency Select: The PSBSEL is tied to the external BSEL resistor-divider
circuitry. The value of the PSBSEL pin reflects the PSB frequency. The PSB runs at
400 MHz when PSBSEL is a 0 and runs at 533 MHz when PSBSEL is a 1.
MEMSEL
I
Memory Configuration Select: This pin selects the SDR or DDR board
configuration. The pin should be unconnected for DDR configuration. For SDR
configuration, a pull-down resistor is required. Refer to the Intel® Pentium® 4
Processor in 478-Pin Package and Intel® 845G/845GL/845GV Chipset Platform
Design Guide for details.
Figure 2-2. Intel® GMCH System Clock and Reset Requirements
RSTIN#
PWROK
~1 ms
POWER
HCLKN/HCLKP
valid
GCLKIN
valid
~100 ms
10 µs
min
10 µs
min



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