845GL datasheet(116/193 Pages) INTEL

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Functional Description

116

Intel® 82845G/82845GL/82845GV GMCH Datasheet

Memory Read Line, and Memory Read Multiple: These commands are treated identically

by the GMCH. The GMCH issues two snoops (a snoop followed by a snoop-ahead) on the host bus

and releases the processor bus for other traffic. When the first DWord of the first cache line is

delivered and GFRAME# is still asserted, the GMCH issues another snoop-ahead on the host bus.

This allows the GMCH to continuously supply data during memory read line and memory read

multiple bursts. When the transaction terminates, there may be a minimum of 2 cache lines and a

maximum of 2 cache lines plus 7 DWords buffered. Subsequent memory reads hitting the buffers

will return data from the buffer.

Memory Write and Memory Write and Invalidate: These commands are aliased and

processed identically. The GMCH supports data streaming for PCI-to-DRAM writes based on its

ability to buffer up to 128 bytes (16 QWords) of data before a snoop cycle must be completed on

the host bus. The GMCH is typically able to support longer write bursts, with the maximum length

dependent upon concurrent host bus traffic during PCI-DRAM write data streaming.

Fast Back-to-Back Transactions: The GMCH, as a target, supports fast back-to-back cycles

from a PCI initiator. As a PCI initiator, the GMCH is responsible for translating host cycles to

AGP/PCI_B cycles. The GMCH also transfers hub interface to AGP/PCI_B write cycles. Table 4-8

shows all the cycles that need to be translated.

Table 4-8. PCI Commands Supported by GMCH When Acting As an AGP/PCI_B Initiator

(Sheet 1 of 2)

Source Bus

Command

Other Encoded Information

GMCH Host Bridge

Corresponding

PCI_B Command

GC/BE[3:0]#

Encoding

Source Bus: Host

Deferred Reply

Don’t Care

None

N/A

Interrupt Acknowledge

Length

≤ 8 Bytes

None

N/A

Special Cycle

Shutdown

None

N/A

Halt

None

N/A

Stop Clock Grant

None

N/A

All Other Combinations

None

N/A

Branch Trace Message

None

N/A

I/O Read

Length

≤ 8 Bytes up to 4 BEx Asserted

I/O Read

0010

I/O Write

Length

≤ 8 Bytes up to 4 BEx Asserted

I/O Write

0011

I/O Read to 0CFCh

Length

≤ 8 Bytes up to 4 BEx Asserted

Configuration Read

1010

I/O Write to 0CFCh

Length

≤ 8 Bytes up to 4 BEx Asserted

Configuration Write

1011

Length

< 8 Bytes without All BEs Asserted

Memory Read

0110

Memory Read (Code or

Data)

Length = 8 Bytes with All BEs Asserted

Memory Read

1110

Memory Read

Invalidate

Length = 16 Bytes

None

N/A

Length = 32 Bytes Code Only

Memory Read

1110

Memory Write

Length

< 8 Bytes without All BEs Asserted

Memory Write

0111

Length = 16 Bytes

None

N/A

Length = 32 Bytes

Memory Write

0111

Locked Access

All Combinations

Unlocked Access1

As Applicable

Reserved Encodings

All Combinations

None

N/A

845GL 데이터시트(PDF) 116 Page - Intel Corporation

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