STM8S datasheet(457/467 Pages) STMICROELECTRONICS

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DocID14587 Rev 14

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RM0016

Revision history

463

10-Aug-2009

cont’d

Changed note in Section 6.9.2: Software priority register x

(ITC_SPRx) on page 69.

Updated AWU Section 12.3.2: Time base selection.

Removed description of timer input XOR feature (TI1S bit in

Section 17 and Section 18.

Updated trigger selection for and ETR description for TIM5 in

Section 18.

Updated MMS bits in Control register 2 (TIM5_CR2) and Control

Updated TG bit of Event generation register (TIMx_EGR).

Added note on TIM2 and TIM4 register offsets inSection on page

247 and Section 19.6.10 on page 260

Section 21.4.3, Acknowledge failure (AF): Added “repeated start” to

master condition.

Modified Section 21.7.3: Frequency register (I2C_FREQR) on

page 307.

Added 6th step to UART Character transmission. Updated

UARTSingle byte communication.

Added Figure 116: TC/TXE behavior when transmitting.

Updated TC bit description in Section 22.7.1: Status register

(UART_SR).

Added Start bit detection and Section 22.3.5: Clock deviation

tolerance of the UART receiver in Section 22.3.3: Receiver.

Added a caution to Section 23.11.15: Mailbox registers.

Updated description of TGT in CAN mailbox data length control

Changed alignment of threshold registers and added note for data

buffer base address in Section 24.11: ADC registers.

08-Dec-2009

Peripheral clock gating register 2 (CLK_PCKENR2): Replaced

address offset.

Table 20: Low power mode management: Updated peripheral

information for Active halt (--), Active halt with MVR auto power off (-

--), and Halt (----).

Repetition counter register (TIM1_RCR): Replaced the reset value.

Interrupt enable register (TIMx_IER): Corrected name of bit 3

(CC3IE) in register table.

Status register 1 (TIMx_SR1): Added description of bit 3 (CC3IF) to

Figure 93: Data clock timing diagram: Removed “from master” and

“from slave” beneath MISO and MOSI respectively.

Section 20.3.5: Data transmission and reception procedures: timing

diagrams revised and description of receive-only mode expanded.

Added Section 20.3.8: Disabling the SPI

Master mode fault (MODF): SPE and MSTR bits can be returned to

their original state only after a MODF bit clearing sequence.

SPI interrupt control register (SPI_ICR): Removed notes relating to

the TXIE and RXIE bits.

Table 79. Document revision history (continued)

Date

Revision

Changes

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