STM8S datasheet(161/467 Pages) STMICROELECTRONICS

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RM0016

16-bit advanced control timer (TIM1)

261

Figure 54 presents an overview of the trigger selection and the master mode selection

blocks.

Figure 54. Trigger/master mode selection blocks

Using one timer as prescaler for another timer

Refer to Figure 55 to see how timer A can be configured to act as a prescaler for timer B.

Configure timer A in master mode so that it outputs a periodic trigger signal on each

UEV. To configure that a rising edge is output on TRGO1 each time an update event is

generated, write MMS = 010 in the TIMx_CR2 register.

Connect the TRGO1 output of timer A to timer B, timer B must be configured in slave

mode using ITR1 as the internal trigger. Select this through the TS bits in the

TIMx_SMCR register (see TS[2:0] bit definitions in TIMx_SMCR register).

Put the clock/trigger controller in external clock mode 1, by writing SMS = 111 in the

TIMx_SMCR register. This causes timer B to be clocked by the rising edge of the

periodic timer A trigger signal (which corresponds to the timer A counter overflow).

Enable both timers by setting their respective CEN bits (TIMx_CR1 register).

Note:

If OCi is selected on timer A as trigger output (MMS = 1xx), its rising edge is used to clock

the counter of timer B.

Figure 55. Master/slave timer example

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