STM8S datasheet(191/467 Pages) STMICROELECTRONICS

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RM0016

16-bit advanced control timer (TIM1)

261

17.7.3

Slave mode control register (TIM1_SMCR)

Address offset: 0x02

Reset value: 0x00

654

3210

MSM

TS[2:0]

Reserved

SMS[2:0]

Bit 7 MSM: Master/slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization

between TIM1 and another timer (through TRGO).

Bits 6:4 TS[2:0]: Trigger selection

This bit field selects the trigger input (TRGI) to be used to synchronize the counter.

000: Internal trigger ITR0 connected to TIM6 TRGO (*)

001: Reserved

010: Reserved

011: Internal trigger ITR3 connected to TIM5 TRGO (*)

100: TI1 edge detector (TI1F_ED)

101: Filtered timer input 1 (TI1FP1)

110: Filtered timer input 2 (TI2FP2)

111: External trigger input (ETRF)

(*): 8K low-density devices only otherwise reserved.

Note: These bits must only be changed when they are not used (e.g. when SMS = 000) to avoid

incorrect edge detections at the transition.

Bit 3 Reserved.

Bits 2:0 SMS[2:0]: Clock/trigger/slave mode selection

When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the

polarity selected on the external input (see input control register and control register description).

000: Clock/trigger controller disabled - If CEN = 1, the prescaler is clocked directly by the internal

clock.

001: Encoder mode 1 - Counter counts up or down on TI2FP2 edge depending on TI1FP1 level

010: Encoder mode 2 - Counter counts up or down on TI1FP1 edge depending on TI2FP2 level

011: Encoder mode 3 - Counter counts up or down on both TI1FP1 and TI2FP2 edges depending on

the level of the other input.

100: Reset mode - Rising edge of the selected trigger signal (TRGI) re-initializes the counter and

generates an update of the registers.

101: Trigger gated mode - The counter clock is enabled when the trigger signal (TRGI) is high. The

counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the

counter are controlled.

110: Trigger standard mode - The counter starts at a rising edge of the trigger TRGI (but, it is not

reset). Only the start of the counter is controlled.

111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter

Note: Trigger gated mode must not be used if TI1F_ED is selected as the trigger input (TS = 100).

TI1F_ED outputs 1 pulse for each transition on TI1F, whereas trigger gated mode checks the

level of the trigger signal.

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