STM8S datasheet(306/467 Pages) STMICROELECTRONICS

306 / 467 page

Inter-integrated circuit (I2C) interface

RM0016

306/467

DocID14587 Rev 14

21.7.2

Control register 2 (I2C_CR2)

Address offset: 0x01

Reset value: 0x00

654

3210

SWRST

Reserved

POS

ACK

STOP

START

Bit 7 SWRST: Software reset

When set, the I2C is at reset state. Before resetting this bit, make sure the I2C lines are released and

the bus is free.

0: I2C Peripheral not at reset state

1: I2C Peripheral at reset state

Note: This bit can be used in case the BUSY bit is set to ‘1’ when no stop condition has been

detected on the bus.

Bits 6::4 Reserved

Bit 3 POS: Acknowledge position (for data reception).

This bit is set and cleared by software and cleared by hardware when PE=0.

0: ACK bit controls the (N)ACK of the current byte being received in the shift register.

1: ACK bit controls the (N)ACK of the next byte which will be received in the shift register.

Note: The POS bit is used when the procedure for reception of 2 bytes (see Method 2: transfer

sequence diagram for master receiver when N=2) is followed. It must be configured before

data reception starts. In this case, to NACK the 2nd byte, the ACK bit must be cleared just after

ADDR is cleared.

Note:

Bit 2 ACK: Acknowledge enable

This bit is set and cleared by software and cleared by hardware when PE=0.

0: No acknowledge returned

1: Acknowledge returned after a byte is received (matched address or data)

Bit 1 STOP: Stop generation

The bit is set and cleared by software, cleared by hardware when a Stop condition is detected, set by

hardware when a timeout error is detected.

– In Master mode:

0: No Stop generation.

1: Stop generation after the current byte transfer or after the current Start condition is sent.

– In Slave mode:

0: No Stop generation.

1: Release the SCL and SDA lines after the current byte transfer.

Bit 0 START: Start generation

This bit is set and cleared by software and cleared by hardware when start is sent or PE=0.

– In Master mode:

0: No Start generation

1: Repeated start generation

– In Slave mode:

0: No Start generation

1: Start generation when the bus is free

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