STM8S datasheet(364/467 Pages) STMICROELECTRONICS

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Universal asynchronous receiver transmitter (UART)

RM0016

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DocID14587 Rev 14

Bit 3 OR: Overrun error(2)

This bit is set by hardware when the word currently being received in the shift register is ready to be

transferred into the RDR register while RXNE=1. An interrupt is generated if RIEN=1 in the

UART_CR2 register. It is cleared by a software sequence (a read to the UART_SR register followed

by a read to the UART_DR register).

0: No Overrun error

1: Overrun error is detected

LHE LIN Header Error (LIN slave mode)

During LIN Header reception, this bit signals three error types:

–

Break delimiter too short

–

Synch Field error

–

Deviation error (if LASE=1)

–

Identifier framing error

0: No LIN Header error

1: LIN Header error detected

Bit 2 NF: Noise flag (3)

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software

sequence (a read to the UART_SR register followed by a read to the UART_DR register).

0: No noise is detected

1: Noise is detected

Bit 1 FE: Framing error (4)

This bit is set by hardware when a de-synchronization, excessive noise or a break character is

detected. It is cleared by a software sequence (a read to the UART_SR register followed by a read

to the UART_DR register).

0: No Framing error is detected

1: Framing error or break character is detected

Note: For the UART2 and UART3, in LIN slave mode (bits LINE and LSLV are set), when a framing

error is detected in the Synch or Identifier Fields , the FE bit is set. But the FE bit will not be set

when a Break reception is detected.

Bit 0 PE: Parity error

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software

sequence (a read to the status register followed by a read to the UART_DR data register). You have

to wait for the RXNE flag to be set before clearing it. An interrupt is generated if PIEN=1 in the

UART_CR1 register.

0: No parity error

1: Parity error (or, in LIN slave mode, identifier parity error)

1. The IDLE bit will not be set again until the RXNE bit has been set itself (i.e. a new idle line occurs)

2. When this bit is set, the RDR register content will not be lost but the shift register will be overwritten.

3. This bit does not generate interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt.

4. This bit does not generate interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. If the

word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be

set.

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