STM32H723VG datasheet(150/227 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H723xE/G

150/227

DS13313 Rev 2

6.3.19

Octo-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 75 and Table 77 for OCTOSPI

are derived from tests performed under the ambient temperature, fHCLK frequency and VDD

supply voltage conditions summarized in Table 12: General operating conditions, with the

following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Measurement points are done at CMOS levels: 0.5VDD

•

IO Compensation cell activated.

•

HSLV activated when VDD ≤ 2.5 V

•

VOS level set to VOS0

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics.

Table 74. LPSDR SDRAM Write timings(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Min

Max

Unit

tw(SDCLK)

FMC_SDCLK period

2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data)

Data output valid time

th(SDCLKL _Data)

Data output hold time

td(SDCLKL_Add)

Address valid time

2.5

td(SDCLKL-SDNWE)

SDNWE valid time

th(SDCLKL-SDNWE)

SDNWE hold time

td(SDCLKL- SDNE)

Chip select valid time

1.5(2)(3)

2. Using PC2 I/O adds 4 ns to this timing.

3. Using PC2_C I/O adds 16.5 ns to this timing.

th(SDCLKL- SDNE)

Chip select hold time

td(SDCLKL-SDNRAS)

SDNRAS valid time

th(SDCLKL-SDNRAS)

SDNRAS hold time

td(SDCLKL-SDNCAS)

SDNCAS valid time

td(SDCLKL-SDNCAS)

SDNCAS hold time

0.5

Table 75. OCTOSPI characteristics in SDR mode(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

F(CLK)

OCTOSPI clock frequency

1.71 V < VDD < 3.6 V,

VOS0,

CLOAD = 15 pF

MHz

1.71 V < VDD < 3.6 V,

VOS0, CLOAD =20 pF

2.7 V < VDD < 3.6 V,

VOS0,

CLOAD = 20 pF

140

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