STM32H723VG datasheet(155/227 Pages) STMICROELECTRONICS

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DS13313 Rev 2

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STM32H723xE/G

Electrical characteristics

208

Figure 36. OCTOSPI Hyperbus write timing diagram

6.3.20

Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 78 for Delay Block are derived

from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply

voltage summarized in Table 12: General operating conditions, with the following

configuration:

6.3.21

16-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 79, Table 80 and Table 81 are

derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA

supply voltage conditions summarized in Table 12: General operating conditions.

MSv47734V2

CS#

Access Latency

Latency Count

Command-Address

47:40

39:32

31:24

23:16

15:8

7:0

Dn+1

Host drives DQ[7:0] and Memory drives RWDS

Host drives DQ[7:0] and RWDS

RWDS

DQ[7:0]

tw(CS)

tv(RWDS)

tv(CK)

th(CK)

High = 2x Latency Count

Low = 1x Latency Count

Read Write Recovery

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

Table 78. Delay Block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tinit

Initial delay

900

1300

1900

t∆

Unit Delay

Table 79. 16-bit ADC characteristics(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Analog supply

voltage for ADC

-1.62

3.6

VREF+

Positive

reference

voltage

VDDA ≥ 2 V

1.62

VDDA

VDDA < 2 V

VDDA

VREF-

Negative

reference

voltage

-VSSA

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