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STM32H723VG 데이터시트(PDF) 198 Page - STMicroelectronics

부품명 STM32H723VG
상세설명  32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
PDF  227 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM32H723VG 데이터시트(HTML) 198 Page - STMicroelectronics

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Electrical characteristics
STM32H723xE/G
198/227
DS13313 Rev 2
Figure 53. SAI master timing waveforms
tv(FS)
FS valid time
Master mode, 2.7 V ≤ VDD ≤ 3.6 V
-
11
ns
Master mode, 1.62 V ≤ VDD ≤ 3.6 V
-
15.5
tsu(FS)
FS setup time
Slave mode
2.5
-
th(FS)
FS hold time
Master mode
6
-
Slave mode
0.5
-
tsu(SD_A_MR)
Data input setup time
Master receiver
3
-
tsu(SD_B_SR)
Slave receiver
3.5
-
th(SD_A_MR)
Data input hold time
Master receiver
3.5
-
th(SD_B_SR)
Slave receiver
0
-
tv(SD_B_ST)
Data output valid time
Slave transmitter (after enable edge),
2.7 V ≤ VDD ≤ 3.6 V
-
10.5
Slave transmitter (after enable edge),
1.62 V ≤ VDD ≤ 3.6 V
-12
th(SD_B_ST)
Data output hold time
Slave transmitter (after enable edge)
6.5
-
tv(SD_A_MT)
Data output valid time
Master transmitter (after enable edge),
2.7 V ≤ VDD ≤ 3.6 V
-
10.5
Master transmitter (after enable edge),
1.62 V ≤ VDD ≤ 3.6 V
-
14.5
th(SD_A_MT)
Data output hold time
Master transmitter (after enable edge)
6
-
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
Table 109. SAI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
MS32771V1
SAI_SCK_X
SAI_FS_X
(output)
1/fSCK
SAI_SD_X
(transmit)
tv(FS)
Slot n
SAI_SD_X
(receive)
th(FS)
Slot n+2
tv(SD_MT)
th(SD_MT)
Slot n
tsu(SD_MR)
th(SD_MR)



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