HCS08 datasheet(72/374 Pages) NXP

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Chapter 5 Resets, Interrupts, and System Configuration

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

5.7

Reset, Interrupt, and System Control Registers and Control Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space

are related to reset and interrupt systems.

Refer to the direct-page register summary in Chapter 4, “Memory,” of this data sheet for the absolute

address assignments for all registers. This section refers to registers and control bits only by their names.

A Freescale-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief

descriptions of these bits are provided here, the related functions are discussed in greater detail in

Chapter 3, “Modes of Operation.”

5.7.1

Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes status and control bits, which are used to configure the IRQ function,

report status, and acknowledge IRQ events.

321

IRQPDD

IRQEDG

IRQPE

IRQF

IRQIE

IRQMOD

IRQACK

Reset

000

= Unimplemented or Reserved

Figure 5-2. Interrupt Request Status and Control Register (IRQSC)

Table 5-2. IRQSC Register Field Descriptions

Field

Description

IRQPDD

Interrupt Request (IRQ) Pull Device Disable — This read/write control bit is used to disable the internal pullup

device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.

0 IRQ pull device enabled if IRQPE = 1.

1 IRQ pull device disabled if IRQPE = 1.

IRQEDG

Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or

levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is

sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured

to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor.

0 IRQ is falling edge or falling edge/low-level sensitive.

1 IRQ is rising edge or rising edge/high-level sensitive.

IRQPE

IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can

be used as an interrupt request.

0 IRQ pin function is disabled.

1 IRQ pin function is enabled.

IRQF

IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.

0 No IRQ request.

1 IRQ event detected.

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