HCS08 datasheet(73/374 Pages) NXP

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Chapter 5 Resets, Interrupts, and System Configuration

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

5.7.2

System Reset Status Register (SRS)

This register includes seven read-only status flags to indicate the source of the most recent reset. When a

debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will

be set. Writing any value except 0x55 and 0xAA in sequence to this register address causes the MCU reset

with the source of COP. The reset state of these bits depends on what caused the MCU to reset.

IRQACK

IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).

Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),

IRQF cannot be cleared while the IRQ pin remains at its asserted level.

IRQIE

IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt

request.

0 Interrupt request when IRQF set is disabled (use polling).

1 Interrupt requested whenever IRQF = 1.

IRQMOD

IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level

detection. See Section 5.5.2.2, “Edge and Level Sensitivity,” for more details.

0 IRQ event on falling/rising edges only.

1 IRQ event on falling/rising edges and low/high levels.

543

210

POR

COP

ILOP

LOC

LVD

—

Writing any value to SRS address clears COP watchdog timer.

POR

000

001

LVR:

000

001

Any other

reset:

(1)

U = Unaffected by reset

1 Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding

to sources that are not active at the time of reset will be cleared.

Figure 5-3. System Reset Status (SRS)

Table 5-3. SRS Register Field Descriptions

Field

Description

POR

Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was

ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while

the internal supply was below the LVR threshold.

0 Reset not caused by POR.

1 POR caused reset.

External Reset Pin — Reset was caused by an active-low level on the external reset pin.

0 Reset not caused by external reset pin.

1 Reset came from external reset pin.

Table 5-2. IRQSC Register Field Descriptions (continued)

Field

Description

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