HCS08 datasheet(141/374 Pages) NXP

141 / 374 page

Analog-to-Digital Converter (S08ADC12V1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

141

10.3.2

Status and Control Register 2 (ADCSC2)

The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the

ADC module.

10.3.3

Data Result High Register (ADCRH)

In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion. In 10-bit

mode, ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 10-bit

mode, ADR[11:10] are cleared. When configured for 8-bit mode, ADR[11:8] are cleared.

In 12-bit and 10-bit mode, ADCRH is updated each time a conversion completes except when automatic

compare is enabled and the compare condition is not met. When a compare event does occur, the value is

the addition of the conversion result and the two’s complement of the compare value. In 12-bit and 10-bit

mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result

registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the

intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL.

RADACT

ADTRG

ACFE

ACFGT

Reset:

1 Bits 1 and 0 are reserved bits that must always be written to 0.

Figure 10-4. Status and Control Register 2 (ADCSC2)

Table 10-5. ADCSC2 Register Field Descriptions

Field

Description

ADACT

Conversion Active. Indicates that a conversion is in progress. ADACT is set when a conversion is initiated and

cleared when a conversion is completed or aborted.

0 Conversion not in progress

1 Conversion in progress

ADTRG

Conversion Trigger Select. Selects the type of trigger used for initiating a conversion. Two types of triggers are

selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated

following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion

of the ADHWT input.

0 Software trigger selected

1 Hardware trigger selected

ACFE

Compare Function Enable. Enables the compare function.

0 Compare function disabled

1 Compare function enabled

ACFGT

Compare Function Greater Than Enable. Configures the compare function to trigger when the result of the

conversion of the input being monitored is greater than or equal to the compare value. The compare function

defaults to triggering when the result of the compare of the input being monitored is less than the compare value.

0 Compare triggers when input is less than compare value

1 Compare triggers when input is greater than or equal to compare value

HCS08 데이터시트(PDF) 141 Page - NXP Semiconductors

HCS08 데이터시트(HTML) 141 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL