AT25QL641 datasheet(22/77 Pages) DIALOG

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AT25QL641

DS-25QL641–130E–10/2018

The CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write

Status Register instruction will not be executed. If CS is driven high after the eighth clock, the CMP, QE and SRP1

(Status Register 2) bits are cleared to 0. After CS is driven high, the self- timed Write Status Register cycle commences

for a time duration of t

W (see Table 8-7, AC Electrical Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to

check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the

cycle is finished and ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch

(WEL) bit in Status Register is cleared to 0.

Figure 7-6.

Write Status Register Instruction (SPI Mode)

Figure 7-7.

Write Status Register Instruction (QPI Mode)

7.7

Write Status Register-2 (31h)

The Write Status Register-2 instruction is used to write only non-volatile Status Register-2 bits CMP, QE and SRP1.

A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status

instruction code, and then writing the status register data byte as illustrated in Figure 7-8 and Figure 7-9.

Using t h e Write Status Register-2 (31h) instruction, software can individually access each one-byte Status register via a

different instruction.

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