AT25QL641 datasheet(26/77 Pages) DIALOG

부품명	AT25QL641

상세설명	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

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AT25QL641

DS-25QL641–130E–10/2018

Figure 7-14. Fast Read Dual Output instruction (SPI Mode)

7.12

Fast Read Quad Output (6Bh)

By using four pins (I/O0, I/O1, I/O2, and I/O3), the ‘Fast Read Quad Output’ instruction allows data to be transferred from the

AT25QL641 at four times the rate of standard SPI devices.

A Quad enable of Status Register-2 must be executed before

the device accepts the Fast Read Quad Output instruction (Status register bit QE must equal 1).

The ‘Fast Read Quad Output’ instruction can operate at the highest possible frequency of FR (see Table 8-7, AC

Electrical Characteristics

). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in

Figure 7-15. The dummy clocks allow the internal circuits additional time for setting up the initial address. During the

dummy clocks, the data value on the SO pin is a “don’t care”. However, the I/O0 pin should be high-impedance prior to

the falling edge of the first data out clock.

AT25QL641 데이터시트(PDF) 26 Page - Dialog Semiconductor