SH7041A datasheet(347/923 Pages) RENESAS

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12.2.5

Timer Status Register (TSR)

The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The

MTU has five TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset

or by standby mode. This register is not initialized by a manual reset.

Channel 0: TSR0:

Bit:

—

TCFV

TGFD

TGFC

TGFB

TGFA

Initial value:

R/W:

R/(W)*

Note: * Only 0 writes to clear the flags are possible.

Channels 1, 2: TSR1, TSR2:

Bit:

TCFD

—

TCFU

TCFV

—

TGFB

TGFA

Initial value:

R/W:

R/(W)*

Note: * Only 0 writes to clear the flags are possible.

Channels 3, 4: TSR3, TSR4:

Bit:

TCFD

—

TCFV

TGFD

TGFC

TGFB

TGFA

Initial value:

R/W:

R/(W)*

Note: * Only 0 writes to clear the flags are possible.

• Bit 7—Count Direction Flag (TCFD): This status flag indicates the count direction of the

channel 1, 2, 3, 4 TCNT counters.

This bit is reserved in channel 0. This bit always reads as 1. The write value should always be

Bit 7: TCFD

Description

TCNT counts down

TCNT counts up (initial value)

• Bit 6—Reserved: This bit always reads as 1. The write value should always be 1.

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