SH7041A datasheet(356/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1,

OLSP = 1.

TCNT3 and

TCNT4 values

TGR3A

TGR4A

H'0000

Positive

phase output

Reverse

phase output

TDDR

TCNT4

TCNT3

Time

Active

level

Initial

output

Initial

output

Compare match

output (up count)

Compare match

output (up count)

Compare match

output (down count)

Compare match

output (down count)

Active level

Figure 12.2 Complementary PWM Mode Output Level Example

12.2.12

Timer Gate Control Register (TGCR)

The timer gate control register (TGCR) is an 8-bit read/write register that controls the waveform

output necessary for brushless DC motor control in complementary PWM mode/reset-

synchronized PWM mode. The TGCR is initialized to H'80 by a power-on reset or in the standby

mode. Manual reset does not initialize TGCR. These register settings are ineffective for anything

other than complementary PWM mode/reset-synchronized PWM mode.

Bit:

—

BDC

Initial value:

R/W:

R/W

• Bit 7—Reserved: This bit always reads as 1. The write value should always be 1.

SH7041A 데이터시트(PDF) 356 Page - Renesas Technology Corp

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