전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SH7041A 데이터시트(PDF) 363 Page - Renesas Technology Corp

부품명 SH7041A
상세설명  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A 데이터시트(HTML) 363 Page - Renesas Technology Corp

Back Button SH7041A Datasheet HTML 359Page - Renesas Technology Corp SH7041A Datasheet HTML 360Page - Renesas Technology Corp SH7041A Datasheet HTML 361Page - Renesas Technology Corp SH7041A Datasheet HTML 362Page - Renesas Technology Corp SH7041A Datasheet HTML 363Page - Renesas Technology Corp SH7041A Datasheet HTML 364Page - Renesas Technology Corp SH7041A Datasheet HTML 365Page - Renesas Technology Corp SH7041A Datasheet HTML 366Page - Renesas Technology Corp SH7041A Datasheet HTML 367Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 363 / 923 page
background image
325
Complementary PWM Mode: Three-phase complementary positive and negative PWM
waveforms whose positive and negative phases do not overlap can be obtained using channels 3
and 4. When set for complementary PWM mode, TGR3A, TGR3B, TGR4A, and TGR4B become
output compare registers. The TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins
also automatically become PWM output pins while TCNT3 and TCNT4 become up/down
counters.
12.4.2
Basic Functions
Always select MTU external pin set function using the pin function controller (PFC).
Counter Operation: When a start bit (CST0–CST4) in the timer start register (TSTR) is set to 1,
the corresponding timer counter (TCNT) starts counting. There are two counting modes: a free-
running mode and a periodic mode.
To select the counting operation (figure 12.7):
1.Set bits TPSC2–TPSC0 in the TCR to select the counter clock.At the same time, set bits
CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock.
2.To operate as a periodic counter, set the CCLR2–CCLR0 bits in the TCR to select TGR as a
clearing source for the TCNT.
3.Set the TGR selected in step 2 as an output compare register using the timer I/O control
register (TIOR).
4.Write the desired cycle value in the TGR selected in step 2.
5.Set the CST bit in the TSTR to 1 to start counting.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com