SH7041A datasheet(402/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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제조업체	RENESAS [Renesas Technology Corp]

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• Initial output in complementary PWM mode

In complementary PWM mode, the initial output is determined by the setting of bits OLSN and

OLSP in the timer output control register (TOCR).

This initial output is the PWM pulse non-active level, and is output from when complementary

PWM mode is set with the timer mode register (TMDR) until TCNT4 exceeds the value set in

the dead time register (TDDR). Figure 12.43 shows an example of the initial output in

complementary PWM mode.

An example of the waveform when the initial PWM duty value is smaller than the TDDR

value is shown in figure 12.44.

Timer output control register settings

OLSN bit: 0 (initial output: high; active level: low)

OLSP bit: 0 (initial output: high; active level: low)

TCNT3, 4 value

TGR4A

TDDR

TCNT3

TCNT4

Initial output

Dead time

Time

Active level

TCNT3, 4 count start

(TSTR setting)

Complementary

PWM mode

(TMDR setting)

Positive phase

output

Negative phase

output

Figure 12.43 Example of Initial Output in Complementary PWM Mode (1)

SH7041A 데이터시트(PDF) 402 Page - Renesas Technology Corp