SH7041A datasheet(571/923 Pages) RENESAS

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14.5

Notes on Use

Sections 14.5.1 through 14.5.9 provide information for using the SCI.

14.5.1

TDR Write and TDRE Flags

The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data

from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can

be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is

0, however, the old data stored in TDR will be lost because the data has not yet been transferred to

the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1.

14.5.2

Simultaneous Multiple Receive Errors

Table 14.13 indicates the state of the SSR status flags when multiple receive errors occur

simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the

RDR, so receive data is lost.

Table 14.13 SSR Status Flags and Transfer of Receive Data

SSR Status Flags

Receive Data

Transfer

Receive Error Status

RDRF

ORER

FER

PER

RSR

→ RDR

Overrun error

Framing error

Parity error

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

Overrun error + framing error + parity

error

Notes: O = Receive data is transferred from RSR to RDR.

X = Receive data is not transferred from RSR to RDR.

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