SH7041A datasheet(618/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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제조업체	RENESAS [Renesas Technology Corp]

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16.4.3

Input Sampling and A/D Conversion Time

The mid-speed A/D converter is equipped with a sample and hold circuit. The mid-speed A/D

converter samples input after t

D hours has elapsed since setting the ADST bit of the A/D

control/status register (ADCSR) to 1, then begins conversion. The A/D conversion timing is

shown in table 16.4.

The A/D conversion time, as shown in figure 16.5, includes both t

D and input sampling time. Here,

D is determined by the write timing to ADCSR and is not constant. Thus the conversion time

changes in the range shown in table 16.4.

The conversion time shown in table 16.4 is the time for the first conversion. For the second

conversion and after, the time will be 256 state (fixed) for CKS=0 and 128 state (fixed) for

CKS=1.

(1)

(2)

ADF

t D

t SPL

t CONV

< Key>

(1): Write cycle of ADCSR

(2): Address of ADCSR

Address

Write signal

Input sampling

timing

tD: A/D conversion start delay time

tSPL: Input sampling time

tCONV: A/D conversion time

Figure 16.5 A/D Conversion Timing

SH7041A 데이터시트(PDF) 618 Page - Renesas Technology Corp