SH7041A datasheet(792/923 Pages) RENESAS

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25.3.2

Control Signal Timing

Table 25.5

Control Signal Timing (Conditions: V

CC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%,

CC = VCC ± 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75° C)

Item

Symbol

Min

Max

Unit

Figure

RES rise/fall

RESr, t RESf

—

200

25.4

RES pulse width

RESW

—

cyc

MRES pulse width

MRESW

—

cyc

NMI rise/fall

NMIr, t NMIf

—

200

25.5

RES setup time*

RESS

—

25.4,

MRES setup time*

MRESS

—

25.5

NMI setup time*

NMIS

—

IRQ7–IRQ0 setup time (edge detection)

IRQES

—

IRQ7–IRQ0 setup time (level detection)

IRQLS

—

NMI hold time

NMIH

—

25.5

IRQ7–IRQ0 hold time

IRQEH

—

IRQOUT output delay time

IRQOD

—

25.6

Bus request setup time

BRQS

—

25.7

Bus acknowledge delay time 1

BACKD1

—35

Bus acknowledge delay time 2

BACKD2

—35

Bus three-state delay time

BZD

—35

Note: * The

RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are asynchronous inputs, but

when thesetup times shown here are provided, the signals are considered to have

produced changes at clock rise (for

RES, MRES, BREQ) or clock fall (for NMI and IRQ7–

IRQ0). If the setup times are not provided, recognition is delayed until the next clock rise

or fall.

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