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SH7041A 데이터시트(PDF) 824 Page - Renesas Technology Corp

부품명 SH7041A
상세설명  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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26.3.2
Control Signal Timing
Table 26.5
Control Signal Timing (Conditions: V
CC = 3.0
*1 to 3.6V, AV
CC = 3.0
*1 to 3.6V,
AV
CC = VCC ± 10%, AVref = 3.0
*1 to AV
CC, VSS = AVSS = 0V, Ta = –20 to +75°C)
Item
Symbol
Min
Max
Unit
Figure
RES rise/fall
t
RESr, t RESf
—
200
ns
26.4
RES pulse width
t
RESW
20
—
t
cyc
MRES pulse width
t
MRESW
20
—
t
cyc
NMI rise/fall
t
NMIr, t NMIf
—
200
ns
26.5
RES setup time*
1
t
RESS
100
—
ns
26.4
MRES setup time*
1
t
MRESS
100
—
ns
26.5
NMI setup time (during edge detection)
t
NMIS
100
—
ns
IRQ7–IRQ0 setup time (edge detection)*
2
t
IRQES
100
—
ns
IRQ7–IRQ0 setup time (level detection)*
2
t
IRQLS
100
—
ns
NMI hold time
t
NMIH
50
—
ns
26.5
IRQ7–IRQ0 hold time
t
IRQEH
50
—
ns
IRQOUT output delay time
t
IRQOD
—
50
ns
26.6
Bus request setup time
t
BRQS
35
—
ns
26.7
Bus acknowledge delay time 1
t
BACKD1
—35ns
Bus acknowledge delay time 2
t
BACKD2
—35ns
Bus three state delay time
t
BZD
—35ns
Notes: *1 SH7042/43 ZTAT (excluding A mask) are 3.2V.
*2 The
RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are asynchronous inputs, but
when the setup times shown here are provided, the signals are considered to have
produced changes at clock rise (for
RES, MRES, BREQ) or clock fall (for NMI and
IRQ7–IRQ0). If the setup times are not provided, recognition is delayed until the next
clock rise or fall.



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