SH7041A datasheet(128/923 Pages) RENESAS

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Table 5.3

Exception Processing Vector Table (cont)

Exception Sources

Vector

Numbers

Vector Table Address Offset

Interrupts

IRQ0

H'00000100–H'00000103

IRQ1

H'00000104–H'00000107

IRQ2

H'00000108–H'0000010B

IRQ3

H'0000010C–H'0000010F

IRQ4

H'00000110–H'00000113

IRQ5

H'00000114–H'00000117

IRQ6

H'00000118–H'0000011B

IRQ7

H'0000011C–H'0000011F

On-chip peripheral

module*

255

H'00000120–H'00000124

H'000003FC–H'000003FF

Note: * The vector numbers and vector table address offsets for each on-chip peripheral module

interrupt are given in section 6, Interrupt Controller (INTC), and table 6.3, Interrupt

Exception Processing Vectors and Priorities.

Table 5.4

Calculating Exception Processing Vector Table Addresses

Exception Source

Vector Table Address Calculation

Resets

Vector table address = (vector table address offset)

= (vector number)

× 4

Address errors, interrupts,

instructions

Vector table address = VBR + (vector table address offset)

= VBR + (vector number)

× 4

Notes: 1. VBR: Vector base register

2. Vector table address offset: See table 5.3.

3. Vector number: See table 5.3.

5.2

Resets

Resets have the highest priority of any exception source. There are two types of resets: manual

resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of

the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in

manual resets, they are not.

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