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SH7041A 데이터시트(PDF) 194 Page - Renesas Technology Corp |
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SH7041A 데이터시트(HTML) 194 Page - Renesas Technology Corp |
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194 / 923 page ![]() 156 9.1.2 Block Diagram Figure 9.2 shows a block diagram of the cache. CCR: Cache control register Cache tag Cache controller Cache data Bus state controller External bus interface CCR Cache Figure 9.2 Cache Block Diagram 9.1.3 Register Configuration The cache has one register, which can be used to control the enabling or disabling of each cache space. The register configuration is shown in table 9.1. |
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