SH7041A datasheet(204/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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10.1.4

The BSC has eight registers. These registers are used to control wait states, bus width, and

interfaces with memories like DRAM, ROM, and SRAM, as well as refresh control. The register

configurations are listed in table 10.2.

All registers are 16 bits. Do not access DRAM space before completing the memory interface

settings. All BSC registers are all initialized by a power-on reset, but are not by a manual reset.

Values are maintained in standby mode.

Table 10.2

Name

Abbr.

R/W

Initial Value Address

Access Size

Bus control register 1

BCR1

R/W

H'200F

H'FFFF8620 8, 16, 32

Bus control register 2

BCR2

R/W

H'FFFF

H'FFFF8622 8, 16, 32

Wait state control register 1

WCR1

R/W

H'FFFF

H'FFFF8624 8, 16, 32

Wait state control register 2

WCR2

R/W

H'000F

H'FFFF8626 8, 16, 32

DRAM area control register

DCR

R/W

H'0000

H'FFFF862A 8, 16, 32

Refresh timer control/status register RTCSR

R/W

H'0000

H'FFFF862C 8, 16, 32

Refresh timer counter

RTCNT

R/W

H'0000

H'FFFF862E 8, 16, 32

Refresh time constant register

RTCOR

R/W

H'0000

H'FFFF8630 8, 16, 32

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