SH7041A datasheet(226/923 Pages) RENESAS

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SH7041A 데이터시트(PDF) 226 Page - Renesas Technology Corp

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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188

10.3.3

CS Assert Period Extension

Idle cycles can be inserted to prevent extension of the

RD signal or WRx signal assert period

beyond the length of the

CSn signal assert period by setting the SW3–SW0 bits of BCR2. This

allows for flexible interfaces with external circuitry. The timing is shown in figure 10.6. Th and Tf

cycles are added respectively before and after the ordinary cycle. Only

CSn is asserted in these

cycles;

RD and WRx signals are not. Further, data is extended up to the T

f cycle, which is

effective for gate arrays and the like, which have slower write operations.

Read

Write

Address

CSn

Data

WRx

Data

DACK

Figure 10.6

CS Assert Period Extension Function

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