SH7041A datasheet(279/923 Pages) RENESAS

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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SAR3

DAR3

Data

buffer

Memory

Transfer source

module

Transfer destination

module

Temporary

buffer

The SAR3 value is taken as the address, memory data is read, and the value is stored in the

temporary buffer. Since the value read at this time is used as the address, it must be 32 bits.

When external connection data bus is 16 bits, two bus cycles are required.

DMAC

SAR3

DAR3

Data

buffer

Memory

Transfer source

module

Transfer destination

module

Temporary

buffer

The value in the temporary buffer is taken as the address, and data is read from the

transfer source module to the data buffer.

SAR3

DAR3

Data

buffer

Memory

Transfer source

module

Transfer destination

module

Temporary

buffer

The DAR3 value is taken as the address, and the value in the data buffer is written to the

transfer destination module.

Note:

Memory, transfer source, and transfer destination modules are shown here.

In practice, connection can be made anywhere there is address space.

DMAC

1st, 2nd bus cycles

3rd bus cycle

4th bus cycle

Figure 11.9 Dual Address Mode and Indirect Address Operation

(When External Memory Space is 16 bits)

SH7041A 데이터시트(PDF) 279 Page - Renesas Technology Corp

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