SH7041A datasheet(297/923 Pages) RENESAS

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SH7041A 데이터시트(PDF) 297 Page - Renesas Technology Corp

부품명	SH7041A

상세설명	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

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Burst Mode, Dual Address, and Edge Detection: In burst mode with dual address and edge

detection,

DREQ sampling is conducted only on the first cycle.

In figure 11.23, DMAC transfer begins, at the earliest, three cycles after the timing of the first

sampling. Thereafter, DMAC transfer continues until the end of the data transfer count set in the

TCR.

DREQ sampling is not conducted during this period. Therefore, DRAK is output on the first

cycle only.

When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput

an edge request. The remaining transfer restarts after the first DRAK output.

The DACK output period in burst mode is the same as in cycle steal mode.

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