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STM8S103F2 데이터시트(PDF) 54 Page - STMicroelectronics |
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STM8S103F2 데이터시트(HTML) 54 Page - STMicroelectronics |
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54 / 121 page ![]() Electrical characteristics STM8S103F2 STM8S103F3 STM8S103K3 54/121 DocID15441 Rev 14 tTEMP Reset release delay VDD rising - - 1.7 ms VIT+ Power-on reset threshold - 2.6 2.7 2.85 V VIT- Brown-out reset threshold - 2.5 2.65 2.8 VHYS(BOR) Brown-out reset hysteresis -- 70 - mV 1. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum operating voltage (VDD min) when the tTEMP delay has elapsed. Table 20. Operating conditions at power-up/power-down (continued) Symbol Parameter Conditions Min Typ Max Unit |
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