STM8S103F2 datasheet(60/121 Pages) STMICROELECTRONICS

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Electrical characteristics

STM8S103F2 STM8S103F3 STM8S103K3

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DocID15441 Rev 14

Total current consumption and timing in forced reset state

Current consumption of on-chip peripherals

Subject to general operating conditions for VDD and TA.

HSI internal RC/fCPU= fMASTER = 16 MHz, VDD = 5 V

Current consumption curves

The following figures show typical current consumption measured with code executing in

RAM.

2. Measured from interrupt event to interrupt vector fetch

3. tWU(WFI) = 2 x 1/fmaster + 67 x 1/fCPU

4. Configured by the REGAH bit in the CLK_ICKR register.

5. Configured by the AHALT bit in the FLASH_CR1 register.

6. Plus 1 LSI clock depending on synchronization.

Table 30. Total current consumption and timing in forced reset state

Symbol

Parameter

Conditions

Typ

Max(1)

1. Guaranteed by design.

Unit

IDD(R)

Supply current in reset

state(2)

Characterized with all I/Os tied to VSS.

VDD = 5 V

400

µA

VDD = 3.3 V

300

tRESETBL

Reset pin release to

vector fetch

150

µs

Table 31. Peripheral current consumption

Symbol

Parameter

Typ

Unit

IDD(TIM1)

TIM1 supply current(1)

1. Data based on a differential IDD measurement between reset configuration and timer counter running at

16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

210

µA

IDD(TIM2)

TIM2 supply current(1)

130

IDD(TIM4)

TIM4 supply current(1)

IDD(UART1) UART1 supply current (2)

2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and

not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not

tested in production.

120

IDD(SPI)

SPI supply current (2)

IDD(I2C)

I2C supply current(2)

IDD(ADC1)

ADC1 supply current when converting(3)

Data based on a differential IDD measurement between reset configuration and continuous A/D

conversions. Not tested in production.

1000

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