 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
STM8S103F2 데이터시트(PDF) 76 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM8S103F2 데이터시트(HTML) 76 Page - STMicroelectronics |
|
|
76 / 121 page  Electrical characteristics STM8S103F2 STM8S103F3 STM8S103K3 76/121 DocID15441 Rev 14 Figure 36. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures Figure 37. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures The reset network shown in Figure 38 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 42: NRST pin characteristics), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
