STM8S103F2 datasheet(78/121 Pages) STMICROELECTRONICS

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Electrical characteristics

STM8S103F2 STM8S103F3 STM8S103K3

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tr(SCK)

tf(SCK)

SPI clock rise and fall

time

Capacitive load:

C = 30 pF

-25

tsu(NSS)(2) NSS setup time

Slave mode

4 * tMASTER

th(NSS)(2) NSS hold time

Slave mode

tw(SCKH)(2)

tw(SCKL)(2)

SCK high and low time

Master mode

tSCK/2 - 15

tSCK/2 + 15

tsu(MI)(2)

tsu(SI)(2)

Data input setup time

Master mode

Slave mode

th(MI)(2)

th(SI)(2)

Data input hold time

Master mode

Slave mode

ta(SO)(2)(3) Data output access time

Slave mode

3* tMASTER

tdis(SO)(2)(4) Data output disable time

Slave mode

tv(SO)(2)

Data output valid time

Slave mode

(after enable edge)

-65

tv(MO)(2)

Data output valid time

Master mode (after

enable edge)

-30

th(SO)(2)

Data output hold time

Slave mode (after

enable edge)

th(MO)(2)

Master mode (after

enable edge)

1. Parameters are given by selecting 10 MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z.

Table 43. SPI characteristics (continued)

Symbol

Parameter

Conditions(1)

Min

Max

Unit

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