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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8770 데이터시트(PDF) 41 Page - Wolfson Microelectronics plc |
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WM8770 데이터시트(HTML) 41 Page - Wolfson Microelectronics plc |
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41 / 52 page  Production Data WM8770 w PD Rev 4.1 June 2005 41 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 RDA3[7:0] 11111111 (0dB) Digital Attenuation Data for Right channel DACR3 in 0.5dB steps. See Table 12 01110 Digital Attenuation DACR3 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. 7:0 LDA4[7:0] 11111111 (0dB) Digital Attenuation Data for Left Channel DACL4 in 0.5dB steps. See Table 12 01111 Digital Attenuation DACL4 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store LDA4 in intermediate latch (no change to output) 1: Store LDA4 and update attenuation on all channels. 7:0 RDA4[7:0] 11111111 (0dB) Digital Attenuation Data for Right Channel DACR4 in 0.5dB steps. See Table 12 10000 Digital Attenuation DACR4 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store RDA4 in intermediate latch (no change to output) 1: Store RDA4 and update attenuation on all channels. 7:0 MASTDA[7:0] 11111111 (0dB) Digital Attenuation Data for all DAC Channels in 0.5dB steps. See Table 12 10001 Master Digital Attenuation (all channels) 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. 10010 Phase swaps 7:0 PHASE 00000000 Controls Phase of DAC Outputs 0: Sets non inverted output phase 1: inverts phase of DAC output 0 DZCEN 0 DAC Digital Volume Zero Cross Enable: 0: Zero Cross detect disabled 1: Zero Cross detect enabled 1 ATC 0 Attenuator Control 0: All DACs use attenuations as programmed. 1: Right channel DACs use corresponding left DAC attenuations 2 IZD 0 Infinite Zero Detection Circuit Control and Automute Control 0: Infinite zero detect automute disabled 1: Infinite zero detect automute enabled 3 TOD 0 DAC Analogue Zero Cross Detect Timeout Disable 0 : Timeout enabled 1: Timeout disabled DAC Output Control PL[3:0] Left Output Right Output PL[3:0] Left Output Right Output 0000 Mute Mute 1000 Mute Right 0001 Left Mute 1001 Left Right 0010 Right Mute 1010 Right Right 0011 (L+R)/2 Mute 1011 (L+R)/2 Right 0100 Mute Left 1100 Mute (L+R)/2 0101 Left Left 1101 Left (L+R)/2 0110 Right Left 1110 Right (L+R)/2 10011 DAC Control 7:4 PL[3:0] 1001 0111 (L+R)/2 Left 1111 (L+R)/2 (L+R)/2 |
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