WM8770 datasheet(43/52 Pages) WOLFSON

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Production Data

WM8770

PD Rev 4.1 June 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

ADCRATE[2:0]

010

Master Mode MCLK:ADCLRC Ratio Select:

010: 256fs

011: 384fs

100: 512fs

ADCOSR

ADC oversample rate select

0: 128x oversampling

1: 64x oversapmling

6:4

DACRATE[2:0]

010

Master Mode MCLK:DACLRC Ratio Select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

10111

Master Mode

Control

Maser/Slave Interface Mode Select

0: Slave Mode – ADCLRC, DACLRC and BCLK are inputs

1: Master Mode – ADCLRC, DACLRC and BCLK are outputs

PWDN

Chip Powerdown Control (works in tandem with ADCD and

DACD):

0: All circuits running, outputs are active

1: All circuits in power save mode, outputs muted

ADCD

ADC Powerdown:

0: ADC enabled

1: ADC disabled

11000

Powerdown

Control

5:2

DACD[3:0]

1111

DAC Powerdown

0: DAC enabled

1: DAC disabled

4:0

LAG[4:0]

01100

(0dB)

Attenuation Data for Left Channel ADC Gain in 1dB steps

MUTE

Mute for Left Channel ADC:

0: Mute off

1: Mute on

LRBOTH

Setting LRBOTH will write the same gain value to LAG[4:0] and

RAG[4:0]

11001

Attenuation

ADCL

ADCMUTE

Mute for Left and Right Channel ADC:

0: Mute off

1: Mute on

4:0

RAG[4:0]

01100

(0dB)

Attenuation Data for Right Channel ADC gain in 1dB steps

MUTE

Mute for Right Channel ADC:

0: Mute off

1: Mute on

11010

Attenuation

ADCR

LRBOTH

Setting LRBOTH will write the same gain value to RAG[4:0] and

LAG[4:0]

2:0

LMX[2:0]

000

ADC left channel input mux control bits

6:4

RMX[2:0]

000

ADC right channel input mux control bits

11011

ADC Mux and

Powerdown

Control

AINPD

Input mux and buffer powerdown

0: Input mux and buffer enabled

1: Input mux and buffer powered down

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