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EB632 데이터시트(PDF) 25 Page - Freescale Semiconductor, Inc |
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EB632 데이터시트(HTML) 25 Page - Freescale Semiconductor, Inc |
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25 / 112 page ![]() HDI16 Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 Freescale Semiconductor 25 Table 18 shows the result of the four kinds of reset on bits in each of the HDI16 registers accessible to the host processor. The hardware reset is caused by asserting the RESET signal. The individual reset is caused by clearing HPCR[HEN]. Table 19 shows the effects of the INIT command in relation to the values of TREQ and RREQ. Table 20 and Table 21 summarize the effect of RREQ and TREQ on the HREQ and HRRQ signals. Table 18. Host-Side Registers After Reset Register Name Register Data Reset Type Hardware (HW) Reset Individual (IR) Reset ICR All Bits 0 — CVR NMI 0 0 HC 0 0 HV[0–6] 0 — ISR HREQ 0 1 if TREQ is set; 0 otherwise HF[4–7] 0 — TRDY 1 1 TXDE 1 1 RXDF 0 0 RX RX[0–3] empty empty TX TX[0–3] empty empty Table 19. Effects of the INIT Command TREQ RREQ After INIT Execution Transfer Direction Initialized 0 0 INIT = 0 None 0 1 INIT = 0; ISR[RXDF] = 0; HSR[HTFE/HTFNF] = 1 Core to host 1 0 INIT = 0; ISR[TXDE] = 1; HSR[HRFF/HRFNE] = 0 Host to core 1 1 INIT = 0; ISR[RXDF] = 0; HSR[HTFE/HTFNF] = 1; ISR[TXDE] = 1; HSR[HRFF/HRFNE] = 0 Host to/from core Table 20. TREQ and RREQ Modes (HDRQ = 0) in Non-DMA Mode (HICR=1) TREQ RREQ HREQ Signal 0 0 No interrupts (polling) 0 1 ISR[RXDF] request (interrupt) 1 0 ISR[TXDE] request (interrupt) 1 1 ISR[RXDF] and ISR[TXDE] request (interrupts) Table 21. TREQ and RREQ Modes (HDRQ = 1) in Non-DMA Mode (HICR=1) TREQ RREQ HTRQ Signal HRRQ Signal 0 0 No interrupts (polling) No interrupts (polling) 0 1 No interrupts (polling) ISR[RXDF] request (interrupt) 1 0 ISR[TXDE] request (interrupt) No interrupts (polling) 1 1 ISR[TXDE] request (interrupt) ISR[RXDF] request (interrupt) |
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