EB632 datasheet(37/112 Pages) FREESCALE

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EFCOP

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Note:

When the counter value is written to the trace buffer, it is shifted one position to the left so the debugger

can use the least significant bit (LSB) to identify a new entry in the trace buffer.

13 EFCOP

The MSC8103 mask set 2K87M does not support an EFCOP module.

14 CPM

The 2K87M CPM adds functionality. The contents of the RISC Controller Configuration Register (RCCR)

changed to accommodate the increased size of the Dual-Port RAM. Support for a ROM-based Inverse Multiplexing

for ATM (IMA) microcode was added. Transmission convergence (TC) layer functionality required to support

IMA was added to the Time-Slot Assigner (TSA). Also, new MCC host commands are added. The following

sections discuss these changes.

14.1 RISC Controller Configuration Register (RCCR) Changes

The 2K87M mask set RISC Controller Configuration (RCCR) expands the Enable RAM Microcode (ERAM) field

from 3 to 4 bits wide (adding RCCR to 19 bit which was reserved in the 2K42A mask set) to reflect the availability

of dual-port RAM space starting at address 0x4000.

RCCR

2K87M Mask Set RISC Controller Configuration Register

0x119C4

Bit

TIME

—

TIMEP

EXT[

1–2]M1

EXT

1P1

—

SCD

EXT

2P1

Type

R/W

Reset

Bit

1617

192021

232425

272829

ERAM

EDM

[1–4]1

EXT[

3–4]M1

EXT

3P1

—

EXT

4P1

Type

R/W

Reset

Notes:

Reserved for future microcode applications

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