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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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EB632 데이터시트(PDF) 58 Page - Freescale Semiconductor, Inc |
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EB632 데이터시트(HTML) 58 Page - Freescale Semiconductor, Inc |
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58 / 112 page  Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 58 Freescale Semiconductor Errata QSIU6 EE[4–5] Pins are Sampled on HRESET,SRESET and PORESET Date Added: 8/31/2000 Description: The EE[4–5] pins should be sampled only on PORESET, but they are sampled on SRESET and HRESET as well. Changing the value of the EE[4–5] pins after PORESET deasser- tion might prevent the chip from booting, because their value might choose a different or unde- fined boot configuration. Workaround: The EE[4–5] values should be kept constant and equal to the values on PORE- SET. 0K40A 1K42A 2K42A QSIU7 Pin IRQ7_INTOUT Not Open Drain Date Added: 9/6/2000 Description: INOUT pin IRQ7_INTOUT should be open-drain but not implemented as one. Workaround: Buffer INTOUT on the board when it is wire ORed. 0K40A 1K42A 2K42A QSIU12 Limited Clock Modes Date Added: 4/2/2001, Modified 2/19/2002 Description: Single-master and Multi-master systems are limited to clock mode 57 for 1K42A and 46 or 57 for 2K42A (see also QSIU14). Note that in mode 46 a 33MHz CLKIN can be used which will result in a 16.5MHz input to the SPLL. Although this is slower than the specified 18MHz (refer to the MSC8101 Data Sheet), this is not an issue in mode 46. 1K42A 2K42A QSIU13 Software Watchdog Cannot be Enabled after Boot from Host Date Added: 8/5/2001 Description: The software watchdog is disabled when booting from host. It cannot be subse- quently enabled because the SYPCR can only be written once. Workaround: None 0K40A 1K42A 2K42A Table 48. Errata Resolved in Mask Set 2K87M (Continued) Errata Number Errata Description Applies to Mask Available 1K42A Clock Modes MODCK BUS:CPM:CORE BUS:CLKIN MAX BUS MAX CPM MAX CORE 57 1:2.5:5 1.0 55 138 275 Available 2K42A Clock Modes MODCK BUS:CPM:CORE BUS:CLKIN MAX BUS MAX CPM MAX CORE 46 1:2:4 2.0 69 138 275 57 1:2.5:5 1.0 55 138 275 |
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