TMPR4955AF datasheet(125/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-53

6.3.13

Data Rate Control

The System interface supports a maximum data rate of one word per cycle, and an external

agent may deliver data to the processor at this maximum data rate. The rate at which data

is delivered to the processor can be controlled by the external agent by driving data and

asserting EValid

EValid

EValid* only when it wants data to be available.

The processor interprets cycles as valid data cycles when EValid

EValid

EValid* is asserted and the

SysCmd bus contains a data identifier. The processor continues to accept data until the end

of data (EOD) indicator is received.

The rate at which the processor transmits data to an external agent is programmed in

the

WBRATE field in G2S Config register. Data patterns are specified using the letters D

and xxxx (D

D indicates a data cycle and xxxx indicates an unused, or idle, cycle). A data pattern is

specified as a sequence of data and unused cycles that will be repeated to provide the

appropriate number of data cycles for a given transfer. For example, a data pattern of

DDxx

DDxx indicates a data rate of two words every four cycles.

TX4955A supports two data rates, D

D and Dxx

Dxx

Dxx. During a cycle indicated by an xxxx, the

processor continues to hold the same data as the previous cycle.

A processor block write request for two words with Dxx pattern is illustrated in Figure

6.3.25; this transaction results from a store doubleword instruction.

EOD

Data

Data 1

Data 0

Write

Addr

812

SysAD

SCycle

SClock

SysCmd

EOK*

PValid*

PMaster*

Figure 6.3.25 Processor Block Write Request With Dxx Data Rate

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