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MPC5200 데이터시트(PDF) 32 Page - Freescale Semiconductor, Inc

부품명 MPC5200
상세설명  Hardware Specifications
PDF  80 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5200 데이터시트(HTML) 32 Page - Freescale Semiconductor, Inc

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MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
32
3.3.7.3
MUXed Mode
Note:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.
2. ACK is input and can be used to shorten the CS pulse width.
Table 26. MUXed Mode Timing
Sym
Description
Min
Max
Units
Notes
SpecID
tCSA
PCI CLK to CS assertion
-
1.8
ns
A7.15
tCSN
PCI CLK to CS negation
-
1.8
ns
A7.16
tALEA
PCI CLK to ALE assertion
-
1
ns
A7.16
t1
ALE assertion before Address, Bank,
TSIZ assertion
-
0.8
ns
A7.17
t2
CS assertion before Address, Bank,
TSIZ negation
-
0.7
ns
A7.18
t3
CS assertion before Data wr valid
-
0.7
ns
A7.19
t4
Data wr hold after CS negation
tIPBIck
-
ns
A7.20
t5
Data rd setup before CS negation
2.8
-
ns
A7.21
t6
Data rd hold after CS negation
0
(DC+1)*tPCIck
ns
1
A7.22
t7
ALE pulse width
-
tPCIck
ns
A7.23
tTSA
CS assertion after TS assertion
-
0.8
ns
A7.24
t8
TS pulse width
-
tPCIck
ns
A7.24
t9
CS pulse width
(2+WS)*tPCIck
(2+WS)*tPCIck
ns
A7.25
tOEA
OE assertion before CS assertion
-
0.4
ns
A7.26
tOEN
OE negation before CS negation
-
0.4
ns
A7.27
t10
RW assertion before ALE assertion
tIPBIck
-
ns
A7.26
t11
RW negation after CS negation
-
tPCIck
ns
A7.27
t12
ACK assertion after CS assertion
tIPBIck
-ns
2
A7.28
t13
ACK negation after CS negation
-
tPCIck
ns
2
A7.28



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