MPC5200 datasheet(18/80 Pages) FREESCALE

18 / 80 page

MPC5200 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

NOTE

Beware of changing the values on the pins of the reset configuration word

after the deassertion of PORRESET. This may cause problems because it

may change the internal clock ratios and so extend the PLL locking process.

3.3.4

External Interrupts

The MPC5200 provides three different kinds of external interrupts:

•

Four IRQ interrupts

•

Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)

•

Eight WakeUp interrupts (special GPIO pins)

The propagation of these three kinds of interrupts to the core is shown in the following graphic:

Figure 4. External interrupt scheme

Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of

external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table

specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock

Distribution Module (see Note Table 16).

Table 16. External interrupt latencies

Interrupt Type

Pin Name

Clock Cycles

Reference Clock

Core Interrupt

SpecID

Interrupt Requests

IRQ0

IP_CLK

critical (cint)

A4.1

IRQ0

IP_CLK

normal (int)

A4.2

IRQ1

IP_CLK

normal (int)

A4.3

IRQ2

IP_CLK

normal (int)

A4.5

IRQ3

IP_CLK

normal (int)

A4.6

8 GPIOs

GPIO WakeUp

GPIO Std

IRQ0

IRQ1

IRQ2

IRQ3

PIs

cint

int

Grouper

Encoder

Main Interrupt

Controller

core_cint

core_int

G2_LE Core

Notes:

1. PIs = Programmable Inputs

2. Grouper and Encoder functions imply programmability in software

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