MPC5200 datasheet(16/80 Pages) FREESCALE

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MPC5200 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

3.3.3

Resets

The MPC5200 has three reset pins:

•PORRESET - Power on Reset

•HRESET - Hard Reset

•SRESET - Software Reset

These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt

trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the DC

Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.

Notes:

1. For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards

its minimum pulse width equals the minimum given for HRESET related to the same reference clock.

2. The tVDD_stable describes the time which is needed to get all power supplies stable.

3. For tlock, refer to the Oscillator/PLL section of this specification for further details.

4. For tup_osc, refer to the Oscillator/PLL section of this specification for further details.

5. Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.

6. The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096

clock cycles.

NOTE

As long as VDD is not stable the HRESET output is not stable.

Table 13. SYS_XTAL_IN Timing

Sym

Description

Min

Max

Units

SpecID

tCYCLE

SYS_XTAL_IN cycle time.1

NOTES:

CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the

resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the

MPC5200 User Manual [1].

28.6

64.1

A2.1

tRISE

SYS_XTAL_IN rise time.

—

5.0

A2.2

tFALL

SYS_XTAL_IN fall time.

—

5.0

A2.3

tDUTY

SYS_XTAL_IN duty cycle (measured at VM).

SYS_XTAL_IN duty cycle is measured at VM.

40.0

60.0

A2.4

CVIH

SYS_XTAL_IN input voltage high

2.0

—

A2.5

CVIL

SYS_XTAL_IN input voltage low

—

0.8

A2.6

Table 14. Reset Pulse Width

Name

Description

Min Pulse Width

Max Pulse

Width

Reference Clock

SpecID

PORRESET

Power On Reset

tVDD_stable+tup_osc+tlock

—

SYS_XTAL_IN

A3.1

HRESET

Hardware Reset

4 clock cycles

—

SYS_XTAL_IN

A3.2

SRESET

Software Reset

4 clock cycles

—

SYS_XTAL_IN

A3.3

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