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MPC5200 데이터시트(PDF) 14 Page - Freescale Semiconductor, Inc

부품명 MPC5200
상세설명  Hardware Specifications
PDF  80 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5200 데이터시트(HTML) 14 Page - Freescale Semiconductor, Inc

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MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
14
3.2.4
G2_LE Core PLL Electrical Characteristics
The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means
of a voltage-controlled core PLL.
3.3
AC Electrical Characteristics
Hyperlinks to the indicated timing specification sections are provided below.
AC Test Timing Conditions:
Unless otherwise noted, all test conditions are as follows:
Table 11. G2_LE PLL Specifications
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
G2_LE frequency
fcore
1
NOTES:
1
The XLB_CLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies.
50
—
550
MHz
O4.1
G2_LE cycle time
tcore
(1)
2.85
—
40.0
ns
O4.2
G2_LE VCO frequency
fVCOcore
(1)
400
—
1200
MHz
O4.3
G2_LE input clock frequency
fXLB_CLK
25
—
367
MHz
O4.4
G2_LE input clock cycle time
tXLB_CLK
2.73
—
50.0
ns
O4.5
G2_LE input clock jitter
tjitter
2
2
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but
the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the
operating frequency.
—
—
150
ps
O4.6
G2_LE PLL relock time
tlock
3
3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
—
—
100
µsO4.7
•
AC Operating Frequency Data
•
USB
•
Clock AC Specifications
•
SPI
•Resets
•MSCAN
•
External Interrupts
•
I2C
•
SDRAM
•
J1850
•PCI
•PSC
•
Local Plus Bus
•
GPIOs and Timers
•
ATA
•
IEEE 1149.1 (JTAG) AC Specifications
•
Ethernet



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